On August 30th, semiconductor giant TSMC's annual Technology Symposium made a triumphant return for the first time in three years. The event showcased a number of exciting technological breakthroughs: first, TSMC's industry-leading 3-nanometer (N3) tech, which is set to enter volume production; second, the next-generation N2 process featuring nanosheet transistors and backside power delivery tech, which is scheduled to begin production in 2025; and third, high-NA EUV scanners made by ASML, which will be brought into the production process in 2024.

A QFII analyst found the most interesting point to be this: How will Dr. Kevin Zhang (張曉強), TSMC's Senior Vice President of Business Development, explain how the nanosheet transistors used in the N2 process can surpass analogous technologies utilized by TSMC’s competitors, such as Samsung and Intel?

Highlight No. 1: N3 process ahead of schedule, N2 technology to be bolstered by three exciting breakthroughs

TSMC CEO Dr. C. C. Wei (魏哲家) explains that the N3 process is set to go into volume production "any day now". Customer response has been so enthusiastic that the engineering team at TSMC has been pushed to the brink in terms of capacity.

"The N2 process will enter mass production in 2025. It is guaranteed to be the smallest, most powerful chip of its generation!"

Zhang came on stage after Wei. He went into detail about the three innovations associated with N2 tech.

First of all, due to changes to the transistor architecture, the N2 process will allow chip designers to increase performance by 10% to 15% at the same power, or reduce power consumption by 25% to 30% at the same frequency.

Second, the N2 process will incorporate brand-new tech: backside power delivery. 

Zhang explains that since high-speed computing relies on lower power consumption in restricted space, it was imperative to integrate many of the chip's features. In addition to revamping the nanochip's architecture, backside power delivery can also make a world of difference, because it allows power to be routed from the back of the wafer, freeing up more space for more interconnects on the front side to deliver better performance.

"This was a technological leap forward, and it was by no means an easy step. We have advanced the craftsmanship of semiconductors both in terms of performance and power efficiency."

Last but not least, TSMC dropped a bombshell: The semiconductor leader is planning to bring high-NA EUV scanners into the production process by 2024.

These machines cost tens of billions of Taiwan dollars each. The cost is almost two times that of the previous generation of scanners. Will they be used for N2 production in 2025?

Zhang declined to comment, saying only that those familiar with optical systems would understand that high-NA EUVs could deliver a larger numerical aperture. This would improve the resolution and make it possible to pattern smaller features in a smaller transistor.

Highlight No. 2: Zhang applauds TSMC for beating his former employer Intel

An analyst points out that seeing as how Zhang is a Chinese national, "It's impressive what he has accomplished at TSMC."

Zhang graduated from Duke University and was an Intel Fellow. He has multiple patents to his name.

Curiously, as Zhang went over TSMC's technological milestones during the Technology Symposium, he spent a good deal of time on the 7-nanometer process developed in 2018, which he touted as "one of the most noteworthy moments in semiconductor history."

It was that year that TSMC surpassed Zhang's former employer, Intel. TSMC broke the world free of Intel's monopoly in the field of advanced processing. IC design companies around the world benefited from this important breakthrough.

Highlight No. 3: TSMC stock price dipped below 500, but Wei took it in stride

On the day of the Symposium, TSMC stocks dipped below 500 at the opening bell. The global recession has hit the electronics industry hard. However, Wei did not seem in the least put out. He exuded confidence about TSMC's ongoing efforts at expansion. He took an aggressive stance in asserting TSMC's technological dominance.

In June this year, Samsung announced that their N3 process has entered volume production ahead of TSMC. But experts believe Samsung may be exaggerating their lead.

Dr. Mark Liu (劉德音), Chairman of TSMC, said three years ago that TSMC's N5 and N3 processes were the real McCoy—an authentic full-node shrink. "What they (the competitors) call 'N3' is closer to TSMC's 'N5'."

For this reason, Wei seemed to be brimming with confidence. Even Dr. Y. L. Wang (王英郎), Vice President of Operations, said this onstage: TSMC is the first in the world to bring the N3 process into mass production.

Morgan Stanley analyst Charlie Chan (詹家鴻) said in a report in August that even Intel will continue to rely on TSMC.

In his report, Chan said TSMC has progressed from 4-nanometer to 3-nanometer tech in 2022. This is "well ahead" of Intel's latest Intel 4 architecture. Even though Intel plans to mass produce the 2-nanometer Intel 20A in 2025, it is possible that Intel's internal manufacturing process would be forced into a situation where they cannot catch up. It would be similar to how Intel still has not caught up with TSMC, and how its N3 process still has not entered volume production.

Chan pointed out that in this scenario, TSMC will be poised to expand rapidly in the next three years. If Intel failed once again to meet its own target, it would have no choice but to outsource CPU production to TSMC and rely on TSMC’s N2 and N3 tech.

Wei was very much at ease when he stressed that while Intel and Samsung could make their own chips, they did not have the client's trust. "They have never succeeded in having both! Whereas at TSMC, we have always succeeded when our customers succeeded."

Have you read?

• How AWSC got its groove back and secured orders from SpaceX 
• How did Taiwan’s Bora Pharmaceuticals acquire an American company twice its size? 
• Taiwan’s ‘hidden champions’ battle to level up 

Translated by Jack Chou
Edited by TC Lin
Uploaded by Ian Huang