Interuniversity Microelectronics Centre (IMEC), the Belgium-based semiconductor research institute, doesn't make chips—but it defines the roadmap the global semiconductor industry follows. TSMC, Samsung, Intel, and ASML are all long-time partners.

In April, IMEC named a new CEO: Patrick Vandenameele, 53.

In May, he hosted the ITF World summit in Antwerp, inviting ASML's CEO along with senior executives from TSMC and Samsung. Nvidia CEO Jensen Huang joined by video.

In late August, IMEC will bring its technology forum to Taiwan for the first time, with Vandenameele set to appear alongside K.C. Hsu (徐國晉), Vice President of Integrated Interconnect & Packaging at TSMC, among others.

TSMC Co-COO and Senior Vice President of Business Development, Dr. Kevin Zhang (張曉強), paid tribute to IMEC in his own keynote at the summit, crediting the institute's pioneering research in new materials and new transistor architectures as a guiding beacon that the industry follows toward mass production. IMEC’s technology roadmap already extends into the early 2040s. 

TSMC Co-Chief Operating Officer Kevin Zhang gave a speech at the forum, revealing the company's future R&D direction. (Photo: Kai-yuan Teng)

At the summit, Vandenameele laid out four vital trends.

Trend One: Demand from AI is Surging

The growth engine in AI is shifting from training to "multi-agentic AI"—systems in which dozens or hundreds of AI agents work together. Vandenameele estimates that moving from training to inference will increase computing workloads 150-fold.This shift changes hardware requirements fundamentally. Memory and logic chips must sit physically closer together. Simply packing in more GPUs is no longer the optimal solution; engineers must design the right computing architecture.

Trend Two: Chip Scaling Enters the "CMOS 2.0" Era

As transistors approach physical limits, planar scaling alone is no longer sufficient. IMEC’s answer is "CMOS 2.0": a next-generation scaling platform that does more than shrink transistors; instead, it stacks transistors with different functions vertically across multiple layers, connected through wafer-to-wafer hybrid bonding, with each layer optimized for a different function. 

IMEC’s latest results show that even a two-layer stack delivers a significant boost in energy efficiency. Under its roadmap, shrinking chips from 2nm to 0.5nm combined with CMOS 2.0 stacking gains could deliver a tenfold performance improvement over the next decade.

Zhang confirmed the direction from a manufacturing standpoint in his own talk, noting that transistor architecture is moving from FinFET to nanosheet, with CFET as the next step. Through transistor scaling, higher density, and 3D stacking, the number of transistors within a single package could increase nearly 50-fold in coming years. But he also acknowledged that the biggest current obstacle to stacking logic chips is that electronic design automation (EDA) tools don't yet support the approach. "The whole ecosystem has to evolve in tandem," he said.

Trend Three: Memory Is Moving Toward the Core

Memory demand from agentic AI is growing explosively, as each AI agent must continuously access and update its own "status" while operating. In traditional architecture, memory sits at the "edge" of a chip, forcing compute units to access data from afar, consuming time and energy. IMEC’s new architecture instead places high-bandwidth memory (HBM) at the center of the compute module.

Zhang also revealed that TSMC is working with DRAM partners to develop technology that stacks DRAM directly atop advanced logic chips. He cited Cerebras, a chipmaker that went public this year, as an early example of this shift: Cerebras worked with TSMC to integrate more than 50 compute chips on a single wafer, paired with large amounts of high-speed SRAM to accelerate inference. This may be the start of memory’s inexorable move toward the core.

Trend Four: Photonic Links Will Replace Copper as AI's Nervous System

As the number of chips in a rack keeps rising, copper cabling is running up against limits on both bandwidth and physical space. "The cables are already too big to fit in the rack," Vandenameele said. The solution is silicon photonics—using light instead of electricity to carry signals. 

With materials science, device design, and 3D integration technology working in concert, interconnect efficiency is expected to improve more than a hundredfold. Pictured is an IMEC lab. (Photo: Kai-yuan Teng)

IMEC’s roadmap aims to push optical connections from between racks to within racks, eventually achieving what is called an "optical highway" inside the interposer itself. Reaching that goal will require boosting interconnect efficiency more than 100-fold—a goal that will depend on coordinated breakthroughs in materials science, device design, and 3D integration. 

Vandenameele illustrated with a metaphor: AI is a violin in an orchestra, but it cannot play alone. Semiconductors are that orchestra. And what IMEC is doing is making sure the orchestra can keep playing alongside AI for decades to come.

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Edited by Jack Chou
Uploaded by Ian Huang