ASML and TSMC are pushing the semiconductor industry toward a major change in one of the most fundamental tools of advanced chipmaking: the photomask. It is also the first time TSMC acknowledges that it intends to use High-NA EUV for advanced chip mass production by 2030.

The companies have launched an industry-wide initiative to develop 12-inch photomasks for High Numerical Aperture (High-NA) EUV lithography, twice the linear dimension of the 6-inch masks that have long been the industry standard. The goal is to establish a 12-inch mask pilot line by 2031 and pave the way for 12-inch High-NA lithography systems to enter advanced-node production around 2033.

The initiative comes as High-NA EUV adoption begins to broaden. Intel has taken an early lead in deploying ASML's next-generation lithography technology, while Samsung plans to introduce High-NA EUV for DRAM production from 2028. TSMC intends to bring the technology into high-volume manufacturing for advanced logic nodes beginning in 2030. It has been hesitant to adopt High-NA EUV and has been using ASML’s more mature lithography machines.

The transition will happen in stages. High-NA EUV will initially operate with today's 6-inch photomasks, allowing chipmakers to adopt the new lithography platform without simultaneously replacing the industry's established mask infrastructure. ASML and TSMC, however, believe an eventual move to larger masks could significantly improve productivity and the economics of High-NA manufacturing.

“We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks,” ASML President and CEO Christophe Fouquet said in the press release.

Why High-NA EUV Matters

EUV lithography has become a critical technology for continued semiconductor scaling, enabling chipmakers to print increasingly fine circuit features while reducing some of the complex multiple-patterning steps required by older lithography technologies.

High-NA EUV takes that capability further by increasing the numerical aperture of the projection optics, providing finer resolution as conventional EUV approaches its practical limits. The technology is becoming increasingly important as transistor architectures grow more complicated and AI processors demand greater computing density and energy efficiency.

TSMC expects the number of layers requiring High-NA EUV to increase as its technology nodes advance, driven primarily by increasingly sophisticated transistor architectures for AI applications.

But High-NA's optical architecture introduces another challenge. The technology uses an anamorphic optical system that magnifies patterns differently in two directions, resulting in a smaller exposure field than conventional EUV when paired with today's standard photomasks.

For sufficiently large chips, manufacturers may therefore need to divide patterns into separate exposure fields and precisely connect them on the wafer through a technique known as stitching. That constraint could become increasingly important as AI and high-performance computing drive chip designers toward larger and more complex dies.

12-Inch Masks Could Boost Productivity by 40%

Moving from 6-inch to 12-inch masks offers a potential solution. The larger format would provide substantially more mask area, enabling future High-NA systems to expose larger patterns without relying as heavily on stitching.

ASML and TSMC say the transition could increase scanner productivity, lower chipmaking costs, and remove stitching constraints, allowing manufacturers to more fully exploit High-NA EUV.

The economic implications could be substantial. ASML Chief Technology Officer Marco Pieters told Reuters that a successful industry transition to larger masks could boost High-NA system productivity by around 40%.

Higher throughput could help offset the rising capital and manufacturing costs associated with leading-edge semiconductor production. It could also strengthen the economic case for using High-NA across more chip layers rather than restricting the technology to layers where its superior resolution is absolutely necessary.

An Entire Ecosystem Must Change

Moving to 12-inch masks, however, involves far more than manufacturing a larger piece of mask substrate.

The semiconductor industry has spent decades building infrastructure around the existing mask standard. Mask writers, inspection systems, metrology equipment, pellicles, cleaning tools and handling equipment may all need to evolve alongside the new format.

Establishing a viable 12-inch standard therefore requires participation across the semiconductor supply chain, explaining why ASML and TSMC are framing the project as an industry-wide initiative rather than a bilateral technology program.

“We have always believed that when the industry works together to solve complex problems, we unlock possibilities that no single company could achieve alone,” TSMC Chairman and CEO C.C. Wei said. Major semiconductor manufacturers, mask suppliers and ecosystem partners attended the initiative's September 7 launch ahead of the SPIE BACUS Conference in Monterey, California.

A Transition Stretching Into the 2030s

The roadmap effectively creates two overlapping technology transitions. Samsung's planned High-NA introduction in 2028 and TSMC's deployment beginning in 2030 will initially rely on conventional 6-inch masks. ASML and its partners then aim to establish a 12-inch photomask pilot line by 2031, followed by 12-inch High-NA systems entering advanced-node production around 2033.

The first transition brings High-NA optics into semiconductor manufacturing while retaining today's mask infrastructure. The second would redesign that ecosystem to extract greater productivity from High-NA and overcome limitations associated with its smaller exposure field.

If successful, the transition could prove particularly important for manufacturing the increasingly large and complex processors underpinning artificial intelligence. The High-NA race is therefore no longer solely about how finely a lithography machine can print. The next challenge is ensuring that increasingly capable—and expensive—systems can manufacture advanced chips at the scale and cost the AI era demands.

Have you read?

• Why Google Is Building Its Own Nvidia
• The Red-Free Challenge: Why the US-Taiwan Autonomous Defense Push Faces an Industrial Reality Check
• SEMICON Taiwan 2026: Micron Counters Rivals, Declares AI Still 'Massively Undersupplied'

Uploaded by Ian Huang